搜索资源列表
LIP1201CORE_dll
- Verilog DLL sOURCE CODE
ahbapb
- AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
New
- amba ahb master decoder
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
AHB_slave-ram
- AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
AHBPAPB
- AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
ACODEH
- AHB总线下的slave ramm的verilog代码 -Verilog code of the AHB bus slave ramm
AMBA_AHB.rar
- amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
AHB
- AMBA - AHB MASTER VERILOG CODE (UNCHECKED)
ahbTestbench_obf
- Verilog AHB Testbench
AHBArbiter
- AMBA ahb总线协议的arbiter模块源代码，verilog编写，适合新手学习使用。-this is a code of AMBA AHB arbiter protocol in verilog
ahb_slave_ssrw
- 通过AHB总线简单访问register/RAM 的verilog 子模块 ssrw stands for simple single read write.- submodule used for simple configuration register/RAM accesses ssrw stands for simple single read write.
ahb_slave
- AHB SLave code in verilog
ahb_master
- AHB master system generator in verilog
ahb_slave_latest.tar
- ahb protocol descr iption and its implementation using verilog -ahb protocol descr iption and its implementation using verilog
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
Ahb2Apb
- AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
ahb_system_generator_latest.tar
- amba ahb master generator by using verilog
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker